1. Field of the Invention
The present invention generally to clock supply devices having a delayed locked loop (DLL), and more particularly to a clock supply device in which a plurality of DLL circuits are arranged in a hierarchical formation.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a conventional clock supply device having DLL circuits arranged in a hierarchical formation. The clock supply device shown in FIG. 1 includes an external clock input terminal for receiving an external clock E-CLK, and a main DLL (M-DLL) circuit 2, which delays the external clock E-CLK. The device includes an internal clock line 3 which is formed of a reciprocating wiring line over which an internal clock I-CLK output by the main DLL circuit 2 is transferred. A symbol NA1 denotes a return point, and symbols NA2 and NA3 denote nodes located in an identical distance measured from the return point NA1.
In the present configuration, the main DLL circuit 2 drives the internal clock I-CLK so that the external clock E-CLK is used as a reference clock and an internal clock I-CLK-N obtained at the return point NA1 on the internal clock line 3 is synchronized with the external clock E-CLK. A phase difference of the internal clock I-CLK-N with respect to the external clock E-CLK is a phase adjusting error -td. The phase adjusting error is a time deviation (error) of a compared clock with respect to the reference clock when assuming that a phase comparator forming the DLL circuit recognizes that the compared clock and the reference clock are in phase with each other.
The clock supply device further includes a local DLL (L-DLL) circuit 4, which compares an internal clock I-CLK-NA2 obtained at the node NA2 with an internal clock I-CLK-NA3 obtained at the node NA3, and produces a local clock L-CLK synchronized with the internal clock I-CLK-NA1 obtained at the return point NA1, that is, the external clock E-CLK. The local DLL circuit 4 recognizes, in terms of the circuit configuration, the internal clock I-CLK-NA3 as being the reference clock and recognizes the internal clock I-CLK-NA1 as being a compared clock. However, the local DLL circuit 4 drives the local clock L-CLK in a state in which the internal clock I-CLK-NA1 is handled as the reference clock and the local clock L-CLK is handled as the compared clock. The phase adjusting error of the local clock L-CLK with respect to the internal clock I-CLK-NA1 is -td.
In short, the conventional clock supply device shown in FIG. 1 is configured so that the DLL circuits 2 and 4 are arranged in the hierarchical formation and the local clock L-CLK synchronized with the external clock E-CLK is output to a circuit which needs a clock synchronized with the external clock E-25 CLK.
FIGS. 2A, 2B and 2C are timing charts of an operation of the conventional clock supply device shown in FIG. 1 and are directed to explaining problems thereof. More particularly, FIG. 2A shows a phase adjusting error of the internal clock I-CLK-NA1 with respect to the external clock E-CLK, and FIG. 2B shows a phase adjusting error of the internal clock I-CLK-NA1 in the local DLL 4. FIG. 2C shows an accumulated value of the phase adjusting errors of the main DLL circuit 2 and the local DLL circuit 4, that is, the phase adjusting error of the local clock L-CLK with respect to the external clock E-CLK.
Since the phase adjusting error of the internal clock I-CLK-NA1 with respect to the external clock E-CLK in the main DLL circuit 2 is -td, as shown in FIG. 2A, the internal clock I-CLK-NA1 is subjected to a delay control so that the rising edge of the internal clock I-CLK-NA1 is located within the range between -td and 0 with respect to the rising edge of the external clock E-CLK.
Since the phase adjusting error of the local clock L-CLK with respect to the internal clock I-CLK-NA1 in the local DLL circuit 4 is -td, as shown in FIG. 2B, the local clock L-CLK is subjected to a delay control so that the rising edge of the local clock L-CLK is located within the range between -td and 0 with respect to the rising edge of the internal clock I-CLK-NA1.
Hence, the accumulated value of the phase adjusting errors of the main DLL circuit 2, that is, the phase adjusting error of the local clock L-CLK with respect to the external clock E-CLK is equal to -2td, as shown in FIG. 2C.
When a clock supply device as described above is mounted on an SDRAM (Synchronous Dynamic Random Access Memory) device and is configured so that the local clock L-CLK is supplied to a data output circuit provided in the SDRAM device, it is required to improve the precision in synchronization of the local clock L-CLK with respect to the external clock E-CLK.